In the semiconductor field, performance demands on complementary metal oxide semiconductor (CMOS) circuits continue to increase. Typically, CMOS circuits comprise n-type FETs (nFETs), which utilize electron carriers for their operation, and p-type FETs (pFETs), which utilize hole carriers for their operation. CMOS circuits are conventionally fabricated on semiconductor wafers (e.g., a silicon wafer) having a single crystal orientation. In particular, most common semiconductor devices have been previously built on silicon wafers having a (100) surface crystal orientation.
Recently, specialty semiconductor substrates have been utilized to improve the performance of the nFETs and pFETs. For example, the strong dependence of carrier mobility on silicon orientation has led to the use of hybrid orientation technology (HOT) or direct silicon bond (DSB) silicon substrates, wherein nFETs are formed in (100) crystal orientation silicon (e.g., the orientation in which electron mobility is higher) and pFETs are formed in (110)-oriented Si (the orientation in which hole mobility is higher.
HOT or DSB semiconductor processing conventionally utilizes amorphization/templated recrystallization (ATR) methods for fabricating hybrid orientation substrates, wherein a first semiconductor layer having a first crystalline orientation is directly bonded to a second semiconductor layer having a second crystalline orientation, wherein the second crystalline orientation differs from the first. Selected areas of the first semiconductor layer are amorphized by ion implantation, and then recrystallized into the orientation of the second semiconductor layer, wherein the second semiconductor layer is used as a crystal template for the recrystallization.
One problem encountered in conventional ATR methods concerns corner defects where the first crystalline orientation meets the second crystalline orientation at or near the surface of the substrate. Such corner defects are believed to be the result of the differing crystal orientations meeting at or near the surface of the substrate, wherein differing speeds of crystal growth and mismatches in lattice constants cause crystalline mismatches in the border region between the first crystalline orientation and the second crystalline orientation.
Attempts to ameliorate such corner or border defects in the past have been made by implementing a high-temperature defect-removal anneal process (e.g., ranging from 1000 C. to 1320 C. and higher), however, such high-temperature anneal processes may be incompatible with advanced lithographic techniques due to thermal stresses associated therewith. Other defect-removal techniques have involved the formation of shallow trench isolation (STI) regions over the defects, thus fully consuming the defects in the STI formation. However, as device sizes continue to become smaller and smaller, the lateral width of the defects may exceed the desired lateral width of the desired STI, thus requiring larger STI widths than desired.